FIG. 1 is a block diagram that illustrates a conventional computer system in which the present invention may be applied. Reference numeral 10 generally indicates the computer system. The computer system 10 includes a host computer 12. The host computer 12 is connected to a storage adapter 14 by means of a peripheral bus 16. The peripheral bus 16 may, for example, be provided in accordance with the PCI (Peripheral Component Interconnect) standard.
A plurality of storage devices 18 (e.g., disk drives) are connected to the storage adapter 14 via a data bus 20. The data bus 20 may, for example, be provided in accordance with the SCSI (Small Computer System Interface) standard.
Each of the storage devices 18 is connected to the data bus 20 via a respective device slot 22. Each device slot 22 includes a bus connection 24 by which the respective storage device 18 is connected to the data bus 20, and a power connection 26 by which a power signal is provided to the respective storage device 18. Although only two storage devices 18 are explicitly shown in FIG. 1 (Device 1 and Device N), it should be understood that the number of storage devices connected to the data bus 20 may be larger. For example, it is customary to connect three, four or more storage devices to a host computer via a single storage adapter.
Also connected to the data bus 20 is an SES (SCSI enclosure services) node 28. The SES node 28 is connected to the device slots 22 via a control bus 30. (The control bus 30 may be provided in accordance with the I2C standard. Instead of the control bus 30, individual control signal connections (not shown) may be provided from the SES node 28 to the device slots 22.) In response to control signals sent to the SES node 28 by the storage adapter 14 over the data bus 20, the SES node 28 controls the device slots 22 to selectively remove power from the storage devices 18. Disabling of the power for the storage devices 18 may take place in connection with, for example, removal and/or replacement of a storage device 18 concurrent with operation of the computer system 10.
Each of the storage adapter 14, the storage devices 18 and the SES node 28 includes a respective bus driver/receiver circuit 32 and an active termination circuit 34. The bus driver/receiver circuits 32 and the active termination circuits 34 are provided to interface the storage adapter 14, the storage devices 18 and the SES node 28 to the data bus 20.
The storage adapter 14 also includes a processor 36 and a memory 38 associated with the processor 36. The memory 38 stores a program (not separately shown) which controls the processor 38 so that the storage adapter 14 performs its functions such as managing the storage devices 18 and the SES node 28.
The active terminations 34 are provided to prevent or minimize reflections of signals coupled to the data bus 20. When an active termination circuit 34 fails, intermittent errors may result. Because of the intermittent nature of such errors, it may be difficult to determine which particular active termination circuit 34 has failed. It is known to examine the errors reported by the computer system 10 and to attempt to infer from the reported errors which component is the source of the errors. This approach frequently fails to isolate the failing component. Consequently, the service provided to the proprietor of the computer system 10 may be less satisfactory than it would otherwise be, and the vendor of the computer system 10 or other party in charge of maintaining the computer system 10 may incur increased costs for service calls. Increased costs may also be incurred for replacement parts, when a component that is not at fault is erroneously replaced. Because of difficulty in identifying a failing component, it is known to take a “shotgun” approach, by replacing numerous parts of the computer system 10 to ensure that the failing component is replaced. This approach leads to additional parts costs for the vendor or service provider, and there remains the possibility that the failing component is not replaced and that further errors and service problems may arise.
It would accordingly be desirable to improve diagnostic procedures that are employed for detecting the source of intermittent errors in computer systems like the computer system 10, and more particularly to improve diagnosis of the source of intermittent errors on a data bus.